In modern computer systems, paging is used for allocating system memory to different devices and processes running on the system. This enables each process to have its own virtual address space that is mapped to an available physical address in the system. Thus, paging requires all memory accesses to go through a translation process to map from a virtual address to a physical address. These address translations are cached in a translation lookaside buffer (TLB) to avoid the need to repeatedly perform a full page walk to perform a translation. A typical paging architecture supports different page sizes in memory (e.g., 4K, 64K, 2M, 1 G pages). Lower granularity is better for higher utilization of physical memory, but results in large number of translations. However, higher granularity results in needing less number of translations (and thus fewer TLB misses and page walks), but suffers from potential low memory utilization since larger amounts of contiguous physical memory are needed for a page allocation.